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general description the MAX9949/max9950 dual parametric measurement units (pmus) feature a small package size, wide force and measurement range, and high accuracy, making the devices ideal for automatic test equipment (ate) and other instrumentation that requires a pmu per pin or per site. the MAX9949/max9950 force or measure voltages in the -2v to +7v through -7v to +13v ranges, dependent upon the supply voltage (v cc and v ee ). the devices handle supply voltages of up to +30v (v cc to v ee ) and a 20v device under test (dut) voltage swing at full cur- rent. the MAX9949/max9950 also force or measure currents up to ?5ma with a lowest full-scale range of ??. integrated support circuitry facilitates use of an external buffer amplifier for current ranges greater than ?5ma. a voltage proportional to the measured output voltage or current is provided at the msr_ output. integrated comparators, with externally set voltage thresholds, pro- vide detection for both voltage and current levels. the msr_ and comparator outputs can be placed in a high- z state. integrated voltage clamps limit the force output to levels set externally. the force-current or the mea- sure-current voltage can be offset -0.2v to +4.4v (ios). this feature allows for the centering of the control or measured signal within the external dac or adc range. the MAX9949d/max9950d feature an integrated 10k ? force-sense resistor between force_ and sense_. the MAX9949f/max9950f have no internal force-sense resistor. these devices are available in a 64-pin 10mm x 10mm, 0.5mm pitch tqfp package with an exposed 8mm x 8mm die pad on the top (MAX9949) or the bottom (max9950) of the package for efficient heat removal. the exposed paddle is internally connected to v ee . the MAX9949/max9950 are specified over the commercial (0? to +70?) temperature range. applications memory testers vlsi testers system-on-a-chip testers structural testers features ? force voltage/measure current (fvmi) ? force current/measure voltage (fimv) ? force voltage/measure voltage (fvmv) ? force current/measure current (fimi) ? force nothing/measure voltage (fnmv) ? five programmable current ranges 2a 20a 200a 2ma 25ma ? -2v to +7v through -7v to +13v input voltage range and higher (up to 20v voltage swing at full current) ? force-current/measure-current voltage offset (ios) ? programmable voltage clamps for the force output ? low-leakage, high-z measure state ? 3-wire serial interface ? low power, 8ma (max) per pmu MAX9949/max9950 dual per-pin parametric measurement units ________________________________________________________________ maxim integrated products 1 ordering information 19-3014; rev 1; 10/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX9949 dccb 0 o c to +70 o c 64 tqfp-epr* MAX9949fccb 0 o c to +70 o c 64 tqfp-epr* max9950 dccb 0 o c to +70 o c 64 tqfp-ep** max9950fccb 0 o c to +70 o c 64 tqfp-ep** part description MAX9949dccb internal 10k ? force-sense resistor MAX9949fccb no internal force-sense resistor max9950dccb internal 10k ? force-sense resistor max9950fccb no internal force-sense resistor selector guide exposed pad is internally connected to v ee . * epr = exposed pad on top. ** ep = exposed pad on bottom. pin configurations appear at end of data sheet.
MAX9949/max9950 dual per-pin parametric measurement units 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +12v, v ee = -7v, v l = +3.3v, t a = t min to t max , unless otherwise noted. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?, unless otherwise specified.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to agnd .......................................................................+20v v ee to agnd.........................................................................-15v v cc to v ee ...........................................................................+32v v l to agnd............................................................................+6v agnd to dgnd.....................................................-0.5v to +0.5v all other pins ...................................(v ee - 0.3v) to (v cc + 0.3v) digital inputs/outputs ...................................-0.3v to (v l + 0.3v) continuous power dissipation (t a = +70 c) 64-pin tqfp-ep (derate 43.5mw/ c above +70 c)....3478mw ja ..............................................................................+23.0?/w jc ..................................................................................+8?/w junction temperature ......................................................+150? storage temperature range .............................-65? to +150? operating temperature (commercial) range ........0? to +70? lead temperature (soldering 10s) ..................................+300? parameter symbol conditions min typ max units force voltage (note 2) force input voltage range v in0 _ , v in1 _ v ee + 3.5v v cc - 3.5v v v cc = +12v, v ee = -7v -2 +7 dut current at full scale v cc = +18v, v ee = - -7 +13 forced voltage v dut dut current = 0 v ee + 3.5v v cc - 3.5v v input bias current ? ? forced-voltage offset error v fos t a = +25? -25 +25 mv forced-voltage offset temperature coefficient ?00 ?/? forced-voltage gain error v fge t a = +25?, nominal gain of +1 -1 0.005 +1 % forced-voltage gain temperature coefficient ?0 ppm/? forced-voltage linearity error v fler t a = +25?, gain and offset errors calibrated out (notes 3, 4) -0.02 +0.02 %fsr measure current (note 2) measure-current offset i mos t a = +25? (note 3) -1 +1 %fsr measure-current offset temperature coefficient ?0 ppm/? measure-current gain error i mge t a = +25? (note 6) -1 +1 % measure-current gain temperature coefficient ?0 ppm/? ranges a? -0.02 +0.02 %fsr linearity error i mler t a = +25?, gain, offset, and common-mode errors calibrated out (notes 3, 4, 5) range e -1 +1 na v ios = v dutgnd -4 +4 measure output voltage range over full current range (note 7) v msr v ios = 4v + v dutgnd 08 v
MAX9949/max9950 dual per-pin parametric measurement units _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = +12v, v ee = -7v, v l = +3.3v, t a = t min to t max , unless otherwise noted. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?, unless otherwise specified.) (note 1) parameter symbol conditions min typ max units current-sense amp offset voltage input v ios relative to v dutgnd -0.2 +4.4 v rejection of output measure error due to common-mode sense voltage cmvr ler specified as the percent of full-scale range change at the measure output per volt change in the dut voltage 0.001 0.007 %fsr/v range e, r_e = 1m ? -2 +2 range d, r_d = 100k ? -20 +20 range c, r_c = 10k ? ? -2 +2 measure current range range a, r_a = 80 ? -25 +25 ma force current (note 2) v ios = v dutgnd -4 +4 input voltage range for setting forced current over full range v ini v ios = 4v + v dutgnd 0+8 v current-sense amp offset voltage input v ios relative to v dutgnd -0.2 +4.4 v v ios input bias current ? ? forced-current offset i fos t a = +25? (note 3) -1 +1 %fsr forced-current offset temperature coefficient ?0 ppm/? forced-current gain error i fge t a = +25? (note 6) -1 +1 % forced-current gain temperature coefficient ?0 ppm/? ranges a? -0.02 +0.02 %fsr forced-current linearity error i fler t a = +25?, gain, offset, and common-mode errors calibrated out (notes 3, 4, 5) range e -1 +1 na rejection of output error due to common-mode load voltage cmri oer specified as the percent of full-scale range change of the forced current per volt change in the dut voltage +0.001 +0.007 %fsr/v range e, r_e = 1m ? -2 +2 range d, r_d = 100k ? -20 +20 range c, r_c = 10k ? ? -2 +2 forced-current range range a, r_a = 80 ? -25 +25 ma measure voltage (note 2) measure-voltage offset v mos t a = +25? -25 +25 mv measure-voltage offset temperature coefficient ?00 ?/? gain error v mger t a = +25?, nominal gain of +1 -1 ?.005 +1 % measure-voltage gain temperature coefficient ?0 ppm/?
MAX9949/max9950 dual per-pin parametric measurement units 4 _______________________________________________________________________________________ dc electrical characteristics (continued) (v cc = +12v, v ee = -7v, v l = +3.3v, t a = t min to t max , unless otherwise noted. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?, unless otherwise specified.) (note 1) parameter symbol conditions min typ max units measure-voltage linearity error v mler t a = +25?, gain and offset errors calibrated out (notes 3, 4, 5) -0.02 +0.02 %fsr v cc = +12v, v ee = -7v -2 +7 dut current at full scale v cc = +18v, v ee = -12v -7 +13 measure output voltage range over full dut voltage (v dut ) v msr dut current = 0v v ee + 3.5v v cc - 3.5v v force output off-state leakage current t a = +25? -5 +5 na i lim- -45 -28 short-circuit current limit i lim+ +28 +45 ma force-to-sense resistor r fs d option only 7.8 10 13.3 k ? sense input input voltage range v ee + 3.5v v cc - 3.5v v leakage current -5 +5 na comparator inputs input voltage range v ee + 3.5v v cc - 3.5v v offset voltage t a = +25? -25 +25 mv input bias current 1a voltage clamps input control voltage v cllo _, v clhi _ v ee + 3.4v v cc - 3.4v v clamp voltage range v ee + 3.5v v cc - 3.5v v clamp voltage accuracy -100 +100 mv digital inputs 5v logic +3.5 3.3v logic +2.0 input high voltage (note 8) v ih 2.7v logic +1.7 v 5v and 3.3v logic +0.8 input low voltage (note 8) v il 2.5v logic +0.7 v input current i in ? ? input capacitance c in 3.0 pf comparator outputs (note 8) output high voltage v oh v l = +2.375v to +5.5v, r pup = 1k ? ?
MAX9949/max9950 dual per-pin parametric measurement units _______________________________________________________________________________________ 5 dc electrical characteristics (continued) (v cc = +12v, v ee = -7v, v l = +3.3v, t a = t min to t max , unless otherwise noted. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?, unless otherwise specified.) (note 1) parameter symbol conditions min typ max units digital outputs (note 8) output high voltage v oh i out = 1ma, v l = +2.375v to +5.5v, relative to dgnd v l - 0.25 v output low voltage v ol i out = -1ma, v l = +2.375v to +5.5v, relative to dgnd 0.2 v power supply positive supply v cc (note 1) +10 +12 +18 negative supply v ee (note 1) -15 -7 -5 v total supply voltage v cc - v ee +30 v logic supply v l +2.375 +5.5 v positive supply current i cc no load, clamps enabled 16.0 ma negative supply current i ee no load, clamps enabled 16.0 ma logic supply current i l no load, all digital inputs at rails 1.2 ma analog ground current i agnd no load, clamps enabled 0.9 ma digital ground current i dgnd no load, all digital inputs at rails 1.4 ma 1mhz, measured at force output 20 power-supply rejection ratio psrr 60hz, measured at force output 85 db ac electrical characteristics (v cc = +12v, v ee = -7v, v l = +3.3v, c cm = 120pf, c l = 100pf, t a = t min to t max , unless otherwise noted. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?, unless otherwise specified.) (note 1) parameter symbol conditions min typ max units force voltage (notes 9, 10) range e, r_e = 1m ? 160 range d, r_d = 100k ? 35 range c, r_c = 10k ? 25 30 range b, r_b = 1k ? 20 settling time range a, r_a = 80 ? 25 ? maximum stable load capacitance 2500 pf force voltage/measure current (notes 9, 10) range e, r_e = 1m ? 480 range d, r_d = 100k ? 50 range c, r_c = 10k ? 35 45 range b, r_b = 1k ? 20 settling time range a, r_a = 80 ? 25 ? range change switching in addition to force-voltage and measure- current settling times, range a to range b, r_a = 80 ? , r_b = 1k ? 10 ?
MAX9949/max9950 dual per-pin parametric measurement units 6 _______________________________________________________________________________________ ac electrical characteristics (continued) (v cc = +12v, v ee = -7v, v l = +3.3v, c cm = 120pf, c l = 100pf, t a = t min to t max , unless otherwise noted. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?, unless otherwise specified.) (note 1) parameter symbol conditions min typ max units force current (notes 9, 10) range e, r_e = 1m ? 300 range d, r_d = 100k ? 100 range c, r_c = 10k ? 40 45 range b, r_b = 1k ? 25 settling time range a, r_a = 80 ? 25 ? force current/measure voltage (notes 9, 10, 11) range e, r_e = 1m ? 1600 range d, r_d = 100k ? 170 range c, r_c = 10k ? 40 50 range b, r_b = 1k ? 25 settling time range a, r_a = 80 ? 25 ? range change switching in addition to force-voltage and measure- current settling times, range a to range b, r_a = 80 ? , r_b = 1k ? 12 ? sense input to measure output path (note 11) settling time c lmsr = 100pf 0.2 ? measure output hiz_ or hizmsr true (0) to high-z c lmsr = 100pf, measured from 50% of digital input voltage to 10% of output voltage 250 ns hiz_ or hizmsr false (1) to active c lmsr = 100pf, measured from 50% of digital input voltage to 90% of output voltage 5s maximum stable load capacitance 1000 pf force output hizforce true (0) to high-z measured from 50% of digital input voltage to 10% of output voltage 2s hizforce false (1) to active measured from 50% of digital input voltage to 90% of output voltage 2s comparators propagation delay 50mv overdrive, 1v p-p , c lcomp = 20pf, r pup = 1k ? measured from input-threshold zero crossing to 50% of output voltage (note 12) 75 ns rise time c lcomp = 20pf, r pup = 1k ? measured from input-threshold zero crossing to 50% of output voltage 60 ns fall time c lcomp = 20pf, r pup = 1k ? , 20% to 80% 5ns
MAX9949/max9950 dual per-pin parametric measurement units _______________________________________________________________________________________ 7 ac electrical characteristics (continued) (v cc = +12v, v ee = -7v, v l = +3.3v, c cm = 120pf, c l = 100pf, t a = t min to t max , unless otherwise noted. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?, unless otherwise specified.) (note 1) parameter symbol conditions min typ max units disable true (0) to high-z c lcomp = 20pf, measured from 50% of digital input voltage to 10% of output voltage 300 ns disable false (1) to active c lcomp = 20pf, measured from 50% of digital input voltage to 90% of output voltage 100 ns serial port (v l = +3.0v, c dout = 10pf) serial clock frequency f sclk 20 mhz sclk pulse-width high t ch 12 ns sclk pulse-width low t cl 12 ns sclk fall to dout valid t do 22 ns cs low to sclk high setup t css0 10 ns sclk high to cs high hold t csh1 22 ns sclk high to cs low hold t csh0 0ns cs high to sclk high setup t css1 5ns din to sclk high setup t ds 10 ns din to sclk high hold t dh (note 13) 0 ns cs pulse-width high t cswh 10 ns cs pulse-width low t cswl 10 ns load pulse-width low t ldw 20 ns v dd high to cs low (power-up) (note 13) 500 ? note 1: the device operates properly with different supply voltages with equally different voltage swings. note 2: tested at v cc = +18v and v ee = -12v. note 3: interpret errors expressed in terms of %fsr (percent of full-scale range) as a percentage of the end-point to end-point range, i.e., for the ?5ma range, the full-scale range = 50ma and a 1% error = 500?. note 4: case must be maintained ?? for linearity specifications. note 5: current linearity specifications are maintained to within 700mv of the clamp voltages when the clamps are enabled. note 6: tested in range c. note 7: linearity of the measured output is only guaranteed within the specified current range. note 8: the digital interface accepts +5v, +3.3v, and +2.5v cmos logic levels. the voltage at v l adjusts the threshold. note 9: settling times are to 0.1% of fsr. cx = 47pf. note 10: all settling times are specified using a single compensation capacitor (cx) across all current-sense resistors. use an indi- vidual capacitor across each sense resistor for better performance across all current ranges, particularly the lower ranges. note 11: the actual settling time of the measured voltage path (sense_ input to msr_ output) is less than 1?. however, the r-c time constant of the sense resistor and the load capacitance causes a longer overall settling time of the dut voltage. this settling time is a function of the current-range resistor used. note 12: the propagation delay time is only guaranteed over the force-voltage output range. propagation delay is measured by holding the sense_ input voltage steady and transitioning thmax_ or thmin_. note 13: guaranteed by design.
MAX9949/max9950 dual per-pin parametric measurement units 8 _______________________________________________________________________________________ typical operating characteristics (v cc = +12v, v ee = -7v, c l = 100pf, r l to +2.5v, range a: r_a = 80 ? , r l = 180 ? ; range b: r_b = 1k ? , r l = 2.25k ? ; range c: r_c = 10k ? , r l = 22.5k ? ; range d: r_d = 100k ? , r l = 225k ? ; range e: r_e = 1m ? , r l = 2.25m ? ,t a = +25 c. transient response fvmi mode ranges a, b, c MAX9949/50 toc01 20 s/div in_ 5v/div 0 0 force_ 5v/div transient response fvmi mode range d MAX9949/50 toc02 100 s/div in_ 5v/div force_ 5v/div 0 0 transient response fvmi mode range e MAX9949/50 toc03 1.0ms/div in_ 5v/div force_ 5v/div 0 0 transient response fvmv mode range c MAX9949/50 toc04 20 s/div in_ 5v/div msr_ 5v/div 0 0 transient response fimi mode ranges a, b, c MAX9949/50 toc05 20 s/div in_ 5v/div force_ 5v/div 0 0 transient response fimi mode range d MAX9949/50 toc06 100 s/div in_ 5v/div force_ 5v/div 0 0 transient response fimi mode range e MAX9949/50 toc07 1.0ms/div in_ 5v/div force_ 5v/div 0 0 ios vs. power supplies MAX9949/50 toc08 voltage (v) 20 -15 -10 -5 0 5 10 15 3.2 1.8 -0.2 -7 4.4 11.2 v ee v cc ios (max) ios (min)
MAX9949/max9950 dual per-pin parametric measurement units _______________________________________________________________________________________ 9 pin max9950 MAX9949 name function 1, 16, 33, 48 1, 16, 33, 48 v ee negative analog supply input 2, 15, 34, 47 2, 15, 34, 47 v cc positive analog supply input 314 rbcom pmu-b range-setting-resistor common connection. connect to one end of all the range- setting resistors (rb_) for pmu-b. also serves as the input to an external current-range buffer for pmu-b. 4 13 rbe pmu-b range e resistor connection 5 12 rbd pmu-b range d resistor connection 6 11 rbc pmu-b range c resistor connection 7 10 rbb pmu-b range b resistor connection 8 9 rba pmu-b range a resistor connection 98 forceb pmu-b driver output. forces a current or voltage to the dut for pmu-b. 10 7 senseb pmu-b sense input. a kelvin connection to the dut. provides the feedback signal in fvmi mode and the measured signal in fimv mode for pmu-b. 11 6 cc1b pmu-b compensation capacitor connection 1. provides compensation for the pmu-b main amplifier. 12 5 cc2b pmu-b compensation capacitor connection 2. provides compensation for the pmu-b main amplifier. 13 4 rxdb pmu-b current-range sense-resistor connection. connects to the external current-range sense resistor on the dut side for pmu-b. see figure 5. 14 3 rxab pmu-b current-range sense-resistor connection. connects to the external current-range sense resistor on the amplifier side for pmu-b. see figure 5. 17 64 cs chip-select input. force cs low to enable communication with the serial port. 18 63 load serial port load input. a logic low asynchronously loads data from the input registers into the pmu registers. 19 62 sclk serial clock input 20 61 din serial data input. data loads into din msb first. 21 60 duthb pmu-b window-comparator high-comparator output. a sense-b voltage above the v thmaxb level forces the duthb output low. duthb is an open-drain output. 22 59 dutlb pmu-b window-comparator low-comparator output. a sense-b voltage below the v thminb level forces the dutlb output low. dutlb is an open-drain output. 23 58 extbsel pmu-b external current-range selector. selects the external current range for pmu-b. 24, 27 54, 57 dgnd digital ground 25 56 dout serial data output. provides data out from the shift register. facilitates daisy-chaining to din of a downstream pmu. dout clocks out data msb first. 26 55 v l logic supply voltage input. the voltage applied at vl sets the upper logic-voltage level. 28 53 extasel pmu-a external current-range selector. selects the external current range for pmu-a. 29 52 dutla pmu-a window-comparator low-comparator output. a sense-a voltage below the v thmina level forces the dutla output low. dutla is an open-drain output. pin description
MAX9949/max9950 dual per-pin parametric measurement units 10 ______________________________________________________________________________________ pin max9950 MAX9949 name function 30 51 dutha pmu-a window-comparator high-comparator output. a sense-a voltage above the v thmaxa level forces the dutha output low. dutha is an open-drain output. 31 50 hi-zb pmu-b msrb output state control. a logic low places the msrb output in a high-impedance state. 32 49 hi-za pmu-a msra output state control. a logic low places the msra output in a high-impedance state. 35 46 rxaa pmu-a current-range sense-resistor connection. connects to the external current-range sense resistor on the amplifier side for pmu-a. see figure 5. 36 45 rxda pmu-a current-range sense-resistor connection. connects to the external current-range sense resistor on the dut side for pmu-a. see figure 5. 37 44 cc2a pmu-a compensation capacitor connection 2. provides compensation for the pmu-a main amplifier. 38 43 cc1a pmu-a compensation capacitor connection 1. provides compensation for the pmu-a main amplifier. 39 42 sensea pmu-a sense input. a kelvin connection to the dut. provides the feedback signal in fvmi mode and the measured signal in fimv mode for pmu-a. 40 41 forcea pmu-a driver output. forces a current or voltage to the dut for pmu-a. 41 40 raa pmu-a range a resistor connection 42 39 rab pmu-a range b resistor connection 43 38 rac pmu-a range c resistor connection 44 37 rad pmu-a range d resistor connection 45 36 rae pmu-a range e resistor connection 46 35 racom pmu-a range-setting-resistor common connection. connect to one end of all range-setting resistors (ra_) for pmu-a. also serves as the input to an external current range buffer for pmu-a. 49 32 thmaxa pmu-a window-comparator upper threshold voltage input. sets the upper voltage threshold for the pmu-a window comparator. 50 31 thmina pmu-a window-comparator lower threshold voltage input. sets the lower voltage threshold for the pmu-a window comparator. 51 30 clhia pmu-a upper clamp voltage input. sets the upper clamp voltage level for pmu-a. 52 29 clloa pmu-a lower clamp voltage input. sets the lower clamp voltage level for pmu-a. 53 28 in0a input voltage 0 for pmu-a. sets the forced current in fi mode or the forced voltage in fv mode for pmu-a. 54 27 in1a input voltage 1 for pmu-a. sets the forced voltage in fv mode or the forced current in fi mode for pmu-a. 55 26 msra pmu-a measurement output. provides a voltage equal to the sense voltage in fimv mode and provides a voltage proportional to the dut current in fvmi mode for pmu-a. force hi-za low to place msra in a high-impedance state. 56 25 ios offset voltage input. sets an offset voltage for the internal current-sense amplifier for both pmu-a and -b. pin description (continued)
detailed description the MAX9949/max9950 force or measure voltages in the -2v to +7v through -7v to +13v ranges, dependent upon the supply voltage range (v cc and v ee ). however, the devices can handle supply voltages up to +30v (v cc to v ee ) and a 20v dut voltage swing at full current. the MAX9949/max9950 pmu also force or measure currents up to ?5ma, with a lowest full-scale range of ??. use an external buffer amplifier for cur- rent ranges greater than ?5ma. the msr_ output presents a voltage proportional to the measured voltage or current. place msr_ in a low-leak- age, high-impedance state by pulling hi-z_ low. integrated comparators with externally programmable voltage thresholds provide ?oo low?( dutl_ ) and ?oo high?( duth_ ) voltage-monitoring outputs. each com- parator output features a selectable high-impedance state. the devices feature separate force_ and sense_ connections and are fully protected against short circuits. the force_ output has two voltage clamps, negative (cllo_) and positive (clhi_), to limit the voltage to externally provided levels. two control voltage inputs, selected independently of the pmu mode, allow for greater flexibility. serial interface the MAX9949/max9950 use a standard 3-wire spi/qspi/microwire-compatible serial port. once the input data register fills, the data becomes avail- able at dout msb first. this data output allows for daisy-chaining multiple devices. figures 1, 2, and 3 show the serial interface timing diagrams. serial port speed the serial port timing specifications are measured at a logic supply voltage (v l ) of +3.0v, ensuring operation of the serial port at rated speed for v l from +3.0v to +5.5v. the serial interface has two ranks. each pmu has an input register that loads from the serial port shift register. each pmu also has a pmu register that loads from the input register. data does not affect the pmu until it reach- es the pmu register. this register configuration permits loading of the pmu data into the input register at one time and then latching the input register data into the pmu register later, at which time the pmu function changes accordingly. the register configuration also provides the ability to change the state of the pmu asynchronously with respect to the loading of that pmu? data into the ser- ial port. thus, the pmu easily updates simultaneously with other pmus or other devices. use the load input to asynchronously load all input registers into the pmu registers. if load remains low when data latches into an input register, the data also transfers to the pmu register. MAX9949/max9950 dual per-pin parametric measurement units ______________________________________________________________________________________ 11 pin max9950 MAX9949 name function 57 24 agnd analog ground 58 23 msrb pmu-b measurement output. provides a voltage equal to the sense voltage in fimv mode and provides a voltage proportional to the dut current in fvmi mode for pmu-b. force hi-zb low to place msrb in a high-impedance state. 59 22 in1b input voltage 1 for pmu-b. sets the forced voltage in fv mode or the forced current in fi mode for pmu-b. 60 21 in0b input voltage 0 for pmu-b. sets the forced current in fi mode or the forced voltage in fi mode for pmu-b. 61 20 cllob pmu-b lower-clamp voltage input. sets the lower clamp voltage level for pmu-b. 62 19 clhib pmu-b upper-clamp voltage input. sets the upper clamp voltage level for pmu-b. 63 18 thminb pmu-b window-comparator lower threshold voltage input. sets the lower voltage threshold for the pmu-b window comparator. 64 17 thmaxb pmu-b window-comparator upper threshold voltage input. sets the upper voltage threshold for the pmu-b window comparator. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor, corp. pin description (continued)
MAX9949/max9950 dual per-pin parametric measurement units 12 ______________________________________________________________________________________ range resistor select in1_ in0_ force_ sense_ rs0_ rs1_ rs2_ f mode_ m mode_ in mode_ sclk 10 to other pmu channel to external current booster for highest range cl enable_ agnd v ee v cc v l r fs* c cm serial interface 1 0 1 0 1 0 ios cc1_ cc2_ dgnd c x extsel_ rxa_ rxd_ dout din cllo_ clhi_ thmin_ thmax_ *rfs internal to MAX9949d/max9950d only hi-zmeas_ cs load msr_ hi-z_ duth_ dutl_ disable_ ra rb rc rd re r_com r_a r_b r_c r_d r_e hi-zforce_ MAX9949 max9950 functional diagram
MAX9949/max9950 dual per-pin parametric measurement units ______________________________________________________________________________________ 13 first bit from previous write sclk din last bit from previous write input register(s) updated dout pmu registers updated load cs d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 figure 1. serial port timing with asynchronous load first bit from previous write sclk din last bit from previous write input and pmu register(s) updated dout load load = 0 cs d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 figure 2. serial port timing with synchronous load
MAX9949/max9950 dual per-pin parametric measurement units 14 ______________________________________________________________________________________ t ldw sclk din d0 d1 d2 d3 d4 d5 d14 d15 t ch t cl t csso t csho t css1 t csh1 t dh t ds t cswh d0last d1last d2last d3last d4last d5last d14last d15last t do dout cs load figure 3. detailed serial port timing diagram shift register /16 control decode input register a input register b pmu register a sclk din to pmua pmu register b to pmub dout load 10 10 10 6 cs figure 4. dual pmu serial port block diagram
bit order the MAX9949/max9950 use the bit order, msb first in and first out, as shown in table 1. pmu control programming both pmus with the same data requires a 16-bit word. programming each pmu with separate data requires two 16-bit words. the address bits specify which input registers the shift register loads. table 2 describes the function of the address bits. bits (c2, c1) specify how the data loads into the second rank pmu registers. these two control bits serve a similar function as the load input. the specified actions occur when cs goes high, whereas the load input loads the pmu register anytime. when either c2 or c1 is low, the corresponding pmu register is transparent. table 3 describes the function of the two control bits. the nop operation requires a1 = a2 = c1 = c2 = 0. in this case, the data transfers through the shift register without changing the state of the MAX9949/max9950. c1 = c2 = 0 allows for data transfer from the shift regis- ter to the input register without transferring data to the pmu register (unless the load input is low). this per- mits the latching of data into the pmu register at a later time by the load input or subsequent command. table 4 summarizes the possible control and address bit combinations. when asynchronously latching only one pmu? data, the input register of the other pmu maintains the same data. therefore, loading both pmu registers would update the one pmu with new data while the other pmu remains in its current state. mode selection four bits from the control word select between the vari- ous modes of operation. in mode selects between the two input analog control voltages. f mode selects whether the pmu forces a voltage or a current. m mode selects whether the dut current or dut voltage is directed to the msr_ output. hi-zforce places the driver amplifier in a high-output impedance state. table 5 describes the various force and measure modes of operation. current-range selection three bits from the control word, rs0, rs1, rs2, con- trol the full-scale current range for either fi (force cur- rent) or mi (measure current). table 6 describes the full-scale current-range control. MAX9949/max9950 dual per-pin parametric measurement units ______________________________________________________________________________________ 15 bit bit name 15 (msb) in mode 14 f mode 13 m mode 12 rs2 11 rs1 10 rs0 9cl enable 8 hi-zforce 7 hi-zmsr 6 disable 5 don? care 4 don? care 3a2 2a1 1c2 0 (lsb) c1 table 1. bit order (bit 3) a2 (bit 2) a1 operation 0 0 do not update any input register (nop). 0 1 only update input register a. 1 0 only update input register b. 11 update both input registers with the same data. table 2. address bit (bit 1) c2 (bit 0) c1 operation 0 0 data stays in input register. 01 transfer pmu-a input register to pmu register. 10 transfer pmu-b input register to pmu register. 11 transfer both input registers to the pmu registers. table 3. control bit
bit (3:2) bit (1:0) a2 a1 c2 c1 pmu-b operation pmu-a operation 0 0 0 0 nop: data just passes through. 0 0 0 1 nop. load pmu register a from input register a. 0 0 1 0 load pmu register b from input register b. nop. 0 0 1 1 load pmu register b from input register b. load pmu register a from input register a. 0 1 0 0 nop. load input register a from shift register. 0 1 0 1 nop. load input register a and pmu register a from shift register. 0 1 1 0 load pmu register b from input register b. load input register a from shift register. 0 1 1 1 load pmu register b from input register b. load input register a and pmu register a from shift register. 1 0 0 0 load input register b from shift register. nop. 1 0 0 1 load input register b from shift register. load pmu register a from input register a. 1010 load input register b and pmu register b from shift register. nop. 1011 load input register b and pmu register b from shift register. load pmu register a from input register a. 1 1 0 0 load input register b from shift register. load input register a from shift register. 1 1 0 1 load input register b from shift register. load input register a and pmu register a from shift register. 1110 load input register b and pmu register b from shift register. load input register a from shift register. 1111 load input register b and pmu register b from shift register. load input register a and pmu register a from shift register. table 4. pmu operation using control and address bits MAX9949/max9950 dual per-pin parametric measurement units 16 ______________________________________________________________________________________ (bit 15) in mode (bit 14) f mode (bit 13) m mode (bit 8) hi-zforce pmu mode force output measure output active input 0001 fvmi voltage i dut v in0 1001 fvmi voltage i dut v in1 0011 fvmv voltage v dut v in0 1011 fvmv voltage v dut v in1 0101 fimi current i dut v in0 1101 fimi current i dut v in1 0111 fimv current v dut v in0 1111 fimv current v dut v in1 xx 0 0 fnmi?eaningless mode xx 1 0 fnmv hi-z v dut x table 5. pmu force/measure mode selection
MAX9949/max9950 dual per-pin parametric measurement units ______________________________________________________________________________________ 17 clamp enable the cl enable bit enables the force-output voltage clamps when high and disables the clamps when low. table 7 depicts the various clamp mode options. measure output high-impedance control the msr_ output attains a low-leakage, high-imped- ance state by using the hi-zmsr control bit or the hi-z_ input. the 2 bits are logically ored together to control the msr_ output. the hi-z_ input allows external multi- plexing among several pmu msr_ outputs without using the serial interface. table 8 explains the various output modes for the msr_ output. digital output (dout) the digital output follows the last output of the serial shift register and clocks out on the falling edge of the input clock. dout provides the first bit of the incoming serial data word 16.5 clock cycles later. this allows for daisy-chaining an additional device using dout and the same clock. ?uick load?using chip select if cs goes low and then returns high without any clock activity, the data from the input registers latch into the pmu registers. this extra function is not standard for spi/qspi/microwire interfaces. the quick load mim- ics the function of load without forcing load low. comparators two comparators configured as a window comparator monitor the msr_ output. thmax_ and thmin_ set the high and low thresholds that determine the window. both outputs are open drain and share a single disable control that places the outputs in a high-z, low-leakage state. table 9 describes the comparator output states of the MAX9949/max9950. (bit 12) rs2 (bit 11) rs1 (bit 10) rs0 range nominal resistor value 0 0 0 ?? r_e = 1m ? 0 0 1 ?? r_e = 1m ? 0 1 0 ?0? r_d = 100k ? 0 1 1 ?00? r_c = 10k ? 1 0 0 ?ma r_b = 1k ? 1 0 1 ?5ma r_a = 80 ? 1 1 0 external 1 1 1 ?5ma r_a = 80 ? table 6. current range selection cl enable mode 1 clamps enabled 0 clamps disabled table 7. clamp enable (bit 7) hi-zmsr hi-z_ msr_ state 11 measure output enabled 0 1 high-z 1 0 high-z 0 0 high-z table 8. msr_ output truth table (bit 6) disable condition duth_ dutl_ 0 x high-z high-z 1v msr > v thmax and v thmin 01 1v thmax > v msr > v thmin 11 1v thmax and v thmin > v msr 10 1v thmin > v msr > v thmax *0 0 table 9. comparator truth table * v thmax > v thmin constitutes normal operation. this condition, however, has v thmin > v thmax and does not cause any problems with the operation of the comparators.
MAX9949/max9950 dual per-pin parametric measurement units 18 ______________________________________________________________________________________ applications information in force-voltage (fv) mode, the output force_ voltage is directly proportional to the input control voltage. in force-current (fi) mode, the current flowing out of the force_ output is proportional to the input control volt- age. positive current flows out of the pmu. in force-nothing (fn) mode, the force_ output is high impedance. in measure-current (mi) mode, the voltage at the msr_ output is directly proportional to the current exiting the force_ output. positive current flows out of the pmu. in measure-voltage (mv) mode, the voltage at the msr_ output is directly proportional to the voltage at the sense_ input. current-sense-amplifier offset voltage input ios is a buffered input to the current-sense amplifier. the current-sense amplifier converts the input control voltage (in0_ or in1_) to the forced dut current (fi) and converts the sensed dut current to the msr_ out- put voltage (mi). when ios equals zero relative to dut- gnd (the gnd voltage at the dut, which the level-setting dacs and the adc are presumed to use as a ground reference), the nominal voltage range that corresponds to full-scale current is -4v to +4v. any voltage applied to the ios input adds directly to this control input/measure output voltage range, i.e., apply- ing +4v to ios forces the voltage range that corre- sponds to full-scale current from 0 to +8v. the following equations determine the minimum and maximum currents for each current range correspond- ing to the input voltage or measure voltage: v maxcurrent = v ios + 4v v mincurrent = v ios - 4v choose ios so the limits of the msr_ output do not go closer than 2.8v to either v ee or v cc . for example, with supplies of +10v and -5v, limit the msr_ output to -2.2v and +7.2v. therefore, set ios between +1.8v and +3.2v. the msr_ output could clip if ios is not within this range. use these general equations for the limits on ios: minimum v ios = v ee + 6.8v maximum v ios = v cc - 6.8v current booster for highest current range an external buffer amplifier can be used to provide a current range greater than the MAX9949/max9950 maximum output current (figure 5). this function oper- ates as follows. a digital output decoded from the range select bits, extsel_, indicates when to activate the booster. the r_com output serves as an input to an external buffer through a 50 ? current-limit series resistor. each side of the external current-sense resistor feeds back to rxa_ and rxd_. ensure that the buffer circuit enters a high-z output state when not selected. any leakage in the buffer adds to the leakage of the pmu. voltage clamps the voltage clamps limit the force_ output and oper- ate over the entire specified current range. set the clamp voltages externally at clhi_ and cllo_. the voltage at the force_ output triggers the clamps inde- pendent of the voltage at the sense_ input. when enabled, the clamps function in both fi and fv modes. current limit the current-limiting circuitry on the force_ output ensures a well-behaved msr_ output for currents between the full current range and the current limits, i.e., for currents greater than the full-scale current, the msr_ voltage is greater than +4v and for currents less than the full-scale current, the msr_ voltage is less than -4v. independent control of the feedback switch and the measure switch two single-pole-double-throw (spdt) switches deter- mine the mode of operation of the pmu. one switch determines whether the sensed dut current or dut voltage feeds back to the input (sensing), and thus force_ r extboost r_com 50 ? rxa_ rxd_ internal to MAX9949/max9950 a v = +2 extsel_ figure 5. external current boost
MAX9949/max9950 dual per-pin parametric measurement units ______________________________________________________________________________________ 19 determines whether the MAX9949/max9950 force cur- rent or voltage. the other switch determines whether the msr_ output senses the dut current or dut voltage. independent control of these switches and the hi-zforce state permits flexible modes of operation beyond the traditional force-voltage/measure-current (fvmi) and force-current/measure-voltage (fimv) modes. the MAX9949/max9950 support the following five modes: fvmi fimv fvmv fimi fnmv figure 6 shows the internal path structure for force-volt- age/measure-current mode. in force-voltage/measure- current mode, the current across the appropriate external sense resistor (r_a to r_e) provides a voltage to the msr_ output. the sense_ input samples the voltage at the dut and feeds the buffered result back to the negative input of the voltage amplifier. the volt- age at msr_ is proportional to the force_ current in accordance with the following formula: v msr _ = i force_ x r sense x 2 figure 7 shows the internal path structure for the force- current/measure-voltage mode. in force-current/mea- sure-voltage mode, the appropriate external sense resistor (r_a to r_e) provides a feedback voltage to the inverting input of the voltage amplifier. the sense_ input samples the voltage at the dut and provides a buffered result at the msr_ output. high-z states the force_, msr_, and comparator outputs feature individual high-z control that places them into a high- impedance, low-leakage state. the high-z state allows busing of msr_ and comparator outputs with other pmu measure and comparator outputs. the force_ output high-z state allows for additional modes of oper- ation as described in table 5 and can eliminate the need for a series relay in some applications. the force_, msr_, and comparator outputs power up in the high-z state. input source selection and gating either one of two input signals, in0_ or in1_, can control both the forced voltage and the forced current. in this case, the two input signals represent alternate forcing values that can be selected with the serial interface. alternatively, each input signal can be dedicated to con- trol a single forcing function (i.e., voltage or current). ground, dut ground, ios the MAX9949/max9950 utilize two local grounds, agnd (analog ground) and dgnd (digital ground). connect agnd and dgnd together on the pc board. in a typical ate system, the pmu force voltage is rela- tive to the dut ground. in this case, reference the input voltages in0_ and in1_ to the dut ground. similarly, reference ios to the dut ground. if it is not desired to offset the current control and measure voltages, con- nect ios to the dut ground potential. reference the msr_ output to the dut ground. figure 6. force-voltage/measure-current functional diagram figure 7. force-current/measure-voltage functional diagram in1_ msr_ a v = +2 dut dutgnd force_ sense_ r sense in1_ a v = +2 dut dutgnd msr_ force_ sense_ r sense
MAX9949/max9950 dual per-pin parametric measurement units 20 ______________________________________________________________________________________ short-circuit protection the force_ output and sense_ input can withstand a short to any voltage between the supply rails. mode and range change transients the MAX9949/max9950 feature make-before-break switching to minimize glitches. the integrated voltage clamps also reduce glitching on the output. dut voltage swing vs. dut current and power-supply voltages several factors limit the actual dut voltage that the pmu delivers: 1) the overhead required by the amplifiers and other integrated circuitry?his is typically 3.5v from each rail for no load current and 5v under full load 2) the voltage drop across the current-range select resistor and internal circuitry in series with the sense resistor?t full current, the combined voltage drop is typically 2.75v 3) variations in the power supplies?ystem implemen- tation determines the variance 4) variation of dut ground vs. pmu ground?ystem implementation determines the variance neglecting the effects of the third and fourth items, figure 8 demonstrates the force output capabilities of the pmu. figure 8 indicates that, for zero dut current, the dut voltage swings from (v ee + 3.5v) to (v cc - 3.5v). for larger positive dut currents, the positive swing drops off linearly until it reaches (v cc - 5v) at full current. similarly, for larger negative dut cur- rents, the negative voltage swing drops off linearly until it reaches (v ee + 5v) at full current. settling times and compensation capacitors the data in the electrical characteristics table reflects the circuit shown in the block diagram that includes a single compensation capacitor (cx) effectively across all the sense resistors. placing individual capacitors, c ra , c rb , c rc , c rd , and c re directly across the sense resistors, r_a, r_b, r_c, r_d, and r_e, independently optimizes each range. the combination of the capacitance across the sense resistors (cx or c ra , c rb , c rc , c rd , and c re ) and the main amplifier compensation comparator, c cm , ensures stability into the maximum expected load capacitance while optimizing settling time. digital inputs (sclk, din, cs , load ) the digital inputs incorporate hysteresis to mitigate issues with noise, as well as provide for compatibility with opto-isolators that can have slow edges. chip information transistor count: 7800 process: bicmos i dut v dut i min i min v ee + 5v v ee + 3.5v v ee - 5v v ee - 3.5v figure 8. pmu force output capability
MAX9949/max9950 dual per-pin parametric measurement units ______________________________________________________________________________________ 21 v cc cc2a rxda rxaa v ee cc1a sensea forcea raa rab rac rad rae racom v cc v ee thmaxb v ee cc2b rxdb rxab v cc cc1b senseb forceb rba rbb rbc rbd rbe rbcom v cc v ee sclk dgnd dgnd din dout thminb clhib cllob in0b in1b msrb agnd ios msra in1a in0a clloa clhia thmina thmaxa extbsel v l extasel 16 15 14 13 12 11 10 9 8 7 5 6 3 4 2 1 24 28 26 27 25 19 23 22 21 20 18 17 31 32 30 29 53 49 50 51 52 58 54 55 56 57 63 59 60 61 62 64 33 34 35 36 37 38 39 40 41 42 43 44 46 45 47 48 cs load duthb dutlb dutla dutha hi-zb hi-za MAX9949 MAX9949 pin configuration
MAX9949/max9950 dual per-pin parametric measurement units maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information for the latest package outline information, go to www.maxim-ic.com/packages . v cc cc2a rxda rxaa v ee cc1a sensea forcea raa rab rac rad rae racom v cc v ee thmaxb v ee cc2b rxdb rxab v cc cc1b senseb forceb rba rbb rbc rbd rbe rbcom v cc v ee sclk dgnd dgnd din dout thminb clhib cllob in0b in1b msrb agnd ios msra in1a in0a clloa clhia thmina thmaxa extbsel v l extasel 16 15 14 13 12 11 10 9 8 7 5 6 3 4 2 1 24 28 26 27 25 19 23 22 21 20 18 17 31 32 30 29 53 49 50 51 52 58 54 55 56 57 63 59 60 61 62 64 33 34 35 36 37 38 39 40 41 42 43 44 46 45 47 48 cs load duthb dutlb dutla dutha hi-zb hi-za max9950 max9950 pin configuration

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